Memory modules come in a variety of configurations depending on a given application and desired storage capacity. For high-capacity memory modules that employ significant numbers of memory devices, a buffered architecture is often preferred. A buffered approach buffers data transferred between the memory devices and a memory controller, thus limiting loading of a data bus to the limited number of buffer devices, rather than the high number of memory devices. Address and control busses are also typically buffered in these systems.
Buffer circuits that are employed in conventional buffered memory modules typically interface with the memory controller and memory devices via respective primary and secondary data paths. The separate sets of data paths may cause an increase in a read-to-write turnaround time, an important timing parameter for modern memory systems.
Thus, the need exists for improved memory modules and associated methods that significantly improve read-to-write turnaround time.